Search results for " CIRCuiTS"
showing 10 items of 187 documents
A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips
2019
Use of bus architecture based communication with increasing processing elements in System-on-Chip (SoC) leads to severe degradation of performance and speed of the system. This bottleneck is overcome with the introduction of Network-on-Chips (NoCs). NoCs assist in communication between cores on a single chip using router based packet switching technique. Due to miniaturization, NoCs like every Integrated circuit is prone to different kinds of faults which can be transient, intermittent or permanent. A fault in any one component of such a crucial network can degrade performance leaving other components non-usable. This paper presents a novel Fault-Tolerant routing Algorithm for Mesh-of-Tree …
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology
2010
Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC). Such decision implies that a certain topology has to be selected to efficiently interconnect many cores on the chip. To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain. However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. This is due to the distinctive features of silicon technology design pitfalls. This work is a first milestone t…
Computer-aided analysis and design procedure for rotating induction machine magnetic circuits and windings
2018
The aim of this study is to present a new, accurate, and user-friendly software procedure for the analysis and rapid design of rotating induction machine windings, considering both the electric and the magnetic specifications of the machine itself. This procedure is a valid aid for quick first stage design without the necessity of using finite element method (FEM)-based design procedures. FEM can be used in a second design phase in order to refine the first stage results. The design procedure is hereafter outlined and some examples show its capability.
Boolean computation in plants using post-translational genetic control and a visual output signal
2018
[EN] Due to autotrophic growing capacity and extremely rich secondary metabolism, plants should be preferred targets of synthetic biology. However, developments in plants usually run below those in other taxonomic groups. In this work we engineered genetic circuits capable of logic YES, OR and AND Boolean computation in plant tissues with a visual output signal. The circuits, which are deployed by means of Agrobacterium tumefaciens, perform with the conditional activity of the MYB transcription factor Roseal from Antirrhinum majus inducing the accumulation of anthocyanins, plant endogenous pigments that are directly visible to the naked eye or accurately quantifiable by spectrophotometric a…
Low-Power, Subthreshold Reference Circuits for the Space Environment : Evaluated with -rays, X-rays, Protons and Heavy Ions
2019
The radiation tolerance of subthreshold reference circuits for space microelectronics is presented. The assessment is supported by measured results of total ionization dose and single event transient radiation-induced effects under &gamma
Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture
2019
This paper outlines a multi-application mapping for Mesh-of-Tree (MoT) topology based Network-on-Chip (NoC) design using reconfigurable architecture. A two phase Particle Swarm Optimization (PSO) has been proposed for reconfigurable architecture to minimize the communication cost. In first phase global mapping is done by combining multiple applications and in second phase, reconfiguration is achieved by switching the cores to near by routers using multiplexers. Experimentations have been carried out for several application benchmarks and synthetic applications generated using TGFF tool. The results show significant improvement in terms of communication cost after reconfiguration.
Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization
2018
As the size of the chip is scaling down the density of Intellectual Property (IP) cores integrated on a chip has been increased rapidly. The communication between these IP cores on a chip is highly challenging. To overcome this issue, Network-on-Chip (NoC) has been proposed to provide an efficient and a scalable communication architecture. In the deep sub-micron level NoCs are prone to faults which can occur in any component of NoC. To build a reliable and robust systems, it is necessary to apply efficient fault-tolerant techniques. In this paper, we present a flexible spare core placement in Mesh-of-Tree (MoT) topology using Particle Swarm Optimization (PSO) by considering IP core failures…
Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement
2018
The increase in the density of the IP cores being fabricated on a chip poses on-chip communication challenges and heat dissipation. To overcome these issues, Network-onChip (NoC) based communication architecture is introduced. In the nanoscale era NoCs are prone to faults which results in performance degradation and un-reliability. Hence efficient fault-tolerant methods are required to make the system reliable in contrast to diverse component failures. This paper presents a flexible spare core placement in torus topology based faulttolerant NoC design. The communications related to the failed core is taken care by selecting the best position for a spare core in the torus network. By conside…
SiC Based Latching Current Limiter for High Voltage Space Power Distribution Systems
2018
This study presents a novel Latching Current Limiter topology, based on a N-channel Silicon Carbide (SiC) MOSFET as the main switching element. The design has been carried out using only discrete components, without digital controllers. This design has been validated by simulation and with a prototype. Tests have been performed at 1000V, modifying the limitation times, current-limiting values and eventually checking the proper operation of the system.
Robust Network Agreement on Logical Information
2011
Abstract Logical consensus is an approach to distributed decision making which is based on the availability of a network of agents with incomplete system knowledge. The method requires the construction of a Boolean map which defines a dynamic system allowing the entire network to consent on a unique, global decision. Previous work by the authors proved the method to be viable for applications such as intrusion detection within a structured environment, when the agent's communication topology is known in advance. The current work aims at providing a fully distributed protocol, requiring no a priori knowledge of each agent's communication neighbors. The protocol allows the construction of a r…